fix: separate rollover correction for gated and ungated clocks#1116
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c-dilks wants to merge 5 commits intodevelopmentfrom
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fix: separate rollover correction for gated and ungated clocks#1116c-dilks wants to merge 5 commits intodevelopmentfrom
c-dilks wants to merge 5 commits intodevelopmentfrom
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Let's close this for now, unless RG-A wants FC charge for Spring 2018 6.5 GeV data. Let's keep the |
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RG-A 6.4 GeV clock issues
Issue 1: Clock frequency is ~125 MHz for most runs:
clas12-timeline) uses a code path which does not use CCDB, rather it uses the hard-coded 1 MHz value; see test: track usage of hard-coded scaler clock frequencies #1128Issue 2: Rollover Structure is different
Notes
This PR, together with changing the clock frequency to the appropriate value, appear to provide a better charge estimate; however, there may still be unknown issues.